Publications - Archive

2008

A Massively Parallel Digital Learning Processor
NIPS 2008
Hans Peter Graf, Srihari Cadambi, Igor Durdanovic, Venkata Jakkula, Murugan Sankaradas, Eric Cosatto, Srimat Chakradhar

Cost Efficient Methods to Improve Performance of Broadcast Scan
ATS 2008, pp. 163-169
Seongmoon Wang, Wenlong Wi

An Efficient Unknown Blocking Scheme for Low Control Data Volume and High Observability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 11, pps. 2039-2052, 2008
Seongmoon Wang, Wenlong Wei

Ram for Free
IEEE Spectrum, pp. 38-43, 2008
L. Yang, R.P. Dick, Haris Lekatsas, Srimat T. Chakradhar

X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactor
IEEE Transactions on Computers, Vol. 57 No. 7, pp. 978-989, 2008
Seongmoon Wang, Kedarnath J. Balakrishnan, Wenlong Wei

Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns
ETS 2008, pp. 125-130, 2008
Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar

IPSec Acceleration using a Programmable Secuirty Processor
DATE 2008, pp. 1147-1153, 2008
J. Thoguluva, Anand Raghunathan

Variation tolerant NoC design by means of self-calibrating links
DATE 2008, pp. 1402-1407, 2008
Simone Medardoni, Marcello Lajolo, David Bertozzi

2007

Rapid Creation of Application Models from Bandwidth Aware Core Graphs
IP 2007
Joao Otero, Marcello Lajolo

A Hybrid Scheme for Compacting Test Responses with Unknown Values
ICCAD 2007, pp. 513-519, 2007
Mango Chia Tso Chao, Kwang Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei

A Low Cost Test Data Compression Technique for High n-Detection Fault Coverage
ITC 2007, pp. 1-10, 2007
Seongmoon Wang, Z. Wang, Wenlong Wei, Srimat T. Chakradhar

A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding
ATS 2007, pp. 79-86, 2007
Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar

Latency Insenstive Design of Heterogeneous Tile Based Networks on Chip
DSD 2007
Marcello Lajolo

Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST
IEEE Transactions on VLSi, pp. 777-789, 2007
Seongmoon Wang

Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation
DAC 2007, pp. 883-886, 2007
M.A. Ghadrat, Kanishka Lahiri, Anand Raghunathan

System-On-Chip Power Management Considering Leakage Variations
DAC 007, pp. 877-882, 2007
S. Chandra, Kanishka Lahiri, Anand Raghunathan, S. Dey

RTL Test Point Insertion to Reduce Delay Test Volume
VLSI Test Symposium 2007
L. Fang, Kedaranath Balakrishnan

Memory-Efficient Regular Expression Search Using State Merging
INFOCOM 2007
Michela Becchi, Srihari Cadambi

Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling
DATE 2007, pp. 39-44, 2007
Q. Zhou, Kedaranath Balakrishnan

Unknown Blocking Scheme for Low Control Data Volume and High Observability
DATE 2007, pp. 33-38, 2007
Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar

Hardware Scheduling Support in SMP Architectures
DATE 2007, pp. 642-647, 2007
A.C. Nacul, Francesco Regazzoni, Marcello Lajolo

SoC Testing Approach LFSR Reseeding and Scan-SliceBased TAM Optimization and Test Scheduling
DATE 2007, pp. 201-206, 2007
Z. Wang, Seongmoon Wang

Hybride Architectures for Efficient and Secure Face Authentication in Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(3):296-308, 2007
N. Aaraj, Srivaths Ravi, Anand Raghunathan

Automatic Energy/performance Macromodeling of Embedded Software
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(3):542-552, 2007
A. Muttreja, Anand Raghunathan, Srivaths Ravi, N.K. Jha

Relationship between Entropy and Test Data Compression
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 26(2):386-395, 2007
Kedarnath J. Balakrishnan, N.A. Toube

A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
ASP-DAC 2007, pp. 810-816, 2007
Seongmoon Wang, Wenlong Wei

Automatic Power Modeling of System-on-Chip Infrastructure IP for System-Level Power Estimation
VLSI 2007, pp. 513-520, 2007
N. Bansal, Kanishka Lahiri, Anand Raghunathan

Zero Cost Test Point Insertion Technique for Structured ASICs
VLSI 2007, pp. 357-363, 2007
R. Sethurap, Seongmoon Wang, Srimat T. Chakradhar, M.L. Bushnell

Efficient Test Compression Using Multiple LFSRs and Dictionary Coding
VLSI 2007, pp. 345-350, 2007
Kedaranath Balakrishnan

2006

Zero Cost Test Point Insertion Technique to Reduce Test Set Sizes and ATPG Run Time for Structured ASICs
ATS 2006, pp. 339-346, 2006
Seongmoon Wang, R. Sethuram, Srimat T. Chakradhar, M.L. Bushnell

A Scalable Synthesis Methodology for Application-Specific Processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(11):1175-1188, 2006
F. Sun, Srivaths Ravi, Anand Raghunathan, N.K. Jha

Considering Process Variations During System-Level Power Analysis
ISLPED 2006, pp. 342-345, 2006
S. Chandra, Kanishka Lahiri, Anand Raghunathan, S. Dey

Use of Computation-Unit Integrated Memories in High-level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(10):1969-1989, 2006
C. Huang, Srivaths Ravi, Anand Raghunathan, N.K. Jha

RTL-Aware Cycle-Accurate Functional Power Estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(10):2103-17, 2006
L. Zhong, Srivaths Ravi, Anand Raghunathan, N.K. Jha

Test-volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(10): 2193-2206, 2006
L. Lingappan, Srivaths Ravi, Anand Raghunathan, N.K. Jha, Srimat T. Chakradhar

C-based Design of a Flexible Wrapper for Tiled Networks on Chip
FDL 2006, pp. 185-188, 2006
Subhek Garg, Marcello Lajolo

Application-specific Custom Heterogeneous Multiprocessor Synthesis Methodology using Extensibe Processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(9):1589-1602, 2006
F. Sun, Srivaths Ravi, Anand Raghunathan, N.K. Jha

Software Architecture Exploration for High-Performance Securty Processing on a Multi-processor Mobile SoC
DAC 2006, pp. 496-401, 2006
D. Arora, Srivaths Ravi, Anand Raghunathan, Murugan Sankaradas, N.K. Jha, Srimat T. Chakradhar

LT-RTPG: A New Test-Per-Scan BIST TPG for Low Switching Activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(8);1565-1574, 2006
Seongmoon Wang, S.K. Gupta

Unknown Tolerance Analysis and Test Quality Control for Test Response Compaction Compactors
DAC 2006, pp. 1083-1088, 2006
Mango Chia Tso Chao, K.T. Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei

Systematic Software-Based Self-Test for Pipelined Processors
DAC 2006, pp. 393-398, 2006
M. Psarakis, D. Gizopoulos, M. Hatzimihail, A. Pashalis, Anand Rathunathan, Srivaths Ravi

UML Modeling and Configuration of Tile Based Networks on Chip
UML-SoC 2006 Sesson of DAC 2006 Workshop, pp. 1-4, 2006
Subhek Garg, Marcello Lajolo

Hardware/Software Codesign of an Operating System
ECRTS 2006, pp. 21-24, 2006
S. Chandra, Francesco Regazzoni, Marcllo Lajolo

Chisel: A Storage-Efficient, Collision-Free Hash-based Packet Processing Architecture
ISCA 2006 - Computer Architecture News, 34(2): 203-215, 2006
J. Hasan, Venkata Jakkula, Srihari Cadambi, Srimat T. Chakradhar

A Design Methodology for Application Specific Networks-on-Chip
ACM Transactions on Embedded Computing Systems, 5(2): 263-280, 2006
J. Xu, W. Wolf, J. Henkel, Srimat T. Chakradhar

Architectural Enhancements for Secure Embedded Processing
Security and Embedded Systems - NATO Security through Science Series - D - Information and Communications Security, Serpanos, Dimitrios, (ed.), IOS Press, 2:18-25, 2006
D. Arora, Srivaths Ravi, Anand Raghunathan, N.K. Jha

A Platform for Designing Secure Embedded Systems
Security and Embedded Systems - NATO Security through Science Series - D - Information and Communications Security, Serpanos, Dimitrios, (ed.), IOS Press, 2:18-25, 2006
Haris Lekatsas, J. Henkel, Venkata Jakkula, Srimat T. Chakradhar

Hardware/Software Partitioning of Operating Systems: a Behavioral Synthesis Approach
GLSVLSI 2006, pp. 324-329, 2006
S. Chandra, Francesco Regazzoni, Marcello Lajolo

A Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software
DATE 2006, pp. 18-23, 2006
N. Potlapally, Anand Raghunathan, Srivaths Ravi, N.K. Jha

Efficient Unknown Blocking Using LFSR Reseeding
DATE 2006, pp. 1051-1052, 2006
Seongmoon Wang, Kedaranath Balakrishnan, Srimat T. Chakradhar

Architectures for Efficient Face Authentication in Embedded Systems
DATE 2006, pp. 1-6, 2006
N. Aaraj, Srivaths Ravi, Anand Raghunathan, N.K. Jha

Coverage Loss by Using Space Compactors in Presence of Unknown Values
DATE 2006, pp. 1053-1054, 2006
Mango Chia Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei

Power Analysis of Mobile 3D Graphics
DATE 2006, pp. 502-508, 2006
B.D. Mochocki, Kanishka Lahiri, Srihari Cadambi

Adaptive Data Placement in an Embedded Multiprocessor Thread Library
DATE 2006, pp. 698-699, 2006
P. Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan

Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms
DATE 2006, pp. 728-733, 2006
K. Sekar, Kanishka Lahiri, Anand Raghunathan, S. Dey

Satisfiability-Based Test Generation for Nonseparable RTL Controller-Datapath Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(3):544-557, 2006
L. Lingappan, Srivaths Ravi, N.K. Jha

Impact of Configurability and Extensibility on IPsec Protocol Execution on Embedded Processors
VLSI 2006, pp. 299-304, 2006
N. Potlapally, Srivaths Ravi, Anand Raghunathan, R. Lee, N.K. Jha

PIDISC: Pattern Independent Design Independent Seed Compression Technique
VLSI 2006, pp. 811-817, 2006
Kedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar

Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems
VLSI 2006, pp. 639-644, 2006
Haris Lekatsas, J. Henkel, Venkata Jakkula, Srimat T. Chakradhar

Hybrid Custom Instruction and Co-processor Synthesis Methodology for Extensible Processors
VLSI 2006, pp. 473-476, 2006
F. Sun, Srivaths Ravi, Anand Raghunathan, N.K. Jha

Interface-Centric Abstraction Level for Rapid Hardware/Software Integration
Applicatons of Specification and Design Languages for SoCs, Vachoux, A. (ed.), Dordrecht, Springer, pp. 83-99, 2006
A.C. Nacul, Marcello Lajolo, T. Givargis

Distance-Based Recent Use (DRU): An Enhancement to Instruction Cache Replacement Policies for Transition Energy Reduction
IEEE Transactions on Very Large Scale Integration Systems - VLSI 14(1):69-80, 2006
P. Kalla, X.S. Hu, J. Henkel

2005

Compressing Functional Tests for Microprocessors
Asian Test Symposium - ATS 05, pp. 428-433, 2005
Kedarnath Balakrishnan, Nur A. Touba, Srinivas Patil

Emerging Techniques for Test Data Compression
Asian Test Symposium - STS 05, pp. 462-467, 2005
Kedaranath Balakrishnan

Hardware/Software Partitioning and Interface Synthesis in Networks On Chip
IP Based SoC Design Conference and Exhibition IP-SOC 2005 pp. 291-296, 2005
Francesco Regazzoni, Marcello Lajolo

Response Shaper: A Novel Technique to Enhance Unknown Tolerance for Output Response Compaction
IEEE/ACM International Conference on Computer-Aided Design '05 - ICCAD '05, pp. 80-87, 2005
Mango C.-T. Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng

XWRC: Externally-loaded Weighted Random Pattern Testing for Input Test Data Compression
International Test Conference - ITC, pp. 571-580, 2005
Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar

Generation of Distributed Logic-memory Architectures through High-Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(11):1694-1711, 2005
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values
IEEE Conference on Computer Design ICCD, pp.147-152, 2005
Mango C.-T. Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng

Interface-Centric Abstraction Level for Rapid Hardware/Software Integration
FORUM on Specification and Design Languages, pp. 329-340, 2005
Andre C. Nacul, Marcello Lajolo, Tony Givargis

Automatic synthesis of the Hardware/Software Interface in Multiprocessor Architectures
Forum on specification and Design Languages - FDL'05, pp. 401-404, 2005
Francesco Ragazzoni, Andre C. Nacul, Marcello Lajolo

SECA : Security-enhanced Communication Architecture
ACM/IEEE Conference on Compilers, Architecture, and Synthesis for Embedded Systems - CASES, pp. 78-89, 2005
Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar

Enhancing Security through Hardware-assisted Run-time Validation of Program Data Properties
ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis pp. 190-195, 2005
Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha

Eliminating Memory Bottlenecks for a JPEG Encoder Through Distributed Logic-Memory Architecture and Computation-unit Integrated Memory
2005 IEEE Custom Integrated Circuits Conference pp. 236-239, 2005
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

CRAMES : Compressed RAM for Embedded Systems
IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis CODES + ISSS 2005, pp. 93-98, 2005
Lei Yang, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar

H.264 HDTV Decoder Using Application-Specific Networks-on-Chip
IEEE Conference on Multimedia and Expo - ICME 2005 pp. 1508-1511, 2005
Jiang Xu, Wayne Wolf, Joerg Henkel, Srimat T. Chakradhar

Hybrid Simulation for Embedded Software Energy Estimation
42nd. Annual ACM/IEEE Conference on Design Automation - DAC 2005 pp. 23-26, 2005
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha

FLEXBUS: A High-Performance System-on-Chip Communication Architecture with a Dynamically Configurable Topology
42nd. Annual ACM/IEEE Conference on Design Automation - DAC 2005 pp. 571-574, 2005
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey

Efficient Fingerprint-based User Authentication for Embedded Systems
42nd. Annual ACM/IEEE Conference on Design Automation -DAC 2005 pp. 244-247, 2005
Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

Power Emulation: A New Paradigm for Power Estimation
42nd. Annual ACM/IEEE Conference on Design Automation 2005 DAC 2005 pp. 700-705, 2005
Joel Coburn, Srivaths Ravi, Anand Raghunathan

Design and Synthesis of Reusable Platforms with Programmable Interconnects
DAC 2005 Workshop, UML-SoC 2005, UML for SoC Design pp. 43-48, 2005
Ananda Shankar Basu, Marcello Lajolo, Mauro Prevostini

Approximate Arithmetic Coding for Bus Transition Reduction in Low Power Designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13(6):696-707, 2005
Haris Lekatsas, Joerg Henkel, Wayne Wolf

A Methodology for Design, Modeling, and Analysis of Networks-on-Chip
IEEE International Symposium on Circuits and Systems, ISCAS 2005 2:1778-81, 2005
Jiang Xu, Wayne Wolf, Joerg Henkel, Srimat T. Chakradhar

SOFTENIT: A Methodology for Boosting the Software Content of System-on-Chip Designs
15th. ACM Great Lakes Symposium on VLSI pp. 361-366, 2005
Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri

Instruction Code Mapping for Performance Increase and Energy Reduction in Embedded Computer systems
IEEE Transactions on Very Large Scale Integration - VLSI 13(4):498-502, 2005
Sri Parameswaran Joerg Henkel

Hardware Accelerated Power Estimation
Design, Automation and Test in Europe Conference and Exhibition - DATE 2005 1:528-529, 2005
Joel Coburn, Srivaths Ravi, Anand Raghunathan

Heterogeneous and Multi-level Compression Techniques for Test Volume Reduction in Systems-on-chip
18th. IEEE International Conference on VLSI Design, VLSI 2005 pp. 65-70, 2005
Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
18th. IEEE International Conference on VLSI Design, VLSI 2005 pp. 575-585, 2005
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar

A Unified Architecture for Adaptive Compression of Data and Code for Embedded Systems
18th. IEEE International Conference on VLSI Design, VLSI 2005 pp. 117-123, 2005
Haris Lekatsas, Joerg Henkel, Venkata Jakkula, Srimat T. Chakradhar

Synthesis of Application-specific Heterogeneous Multiprocessor Architectures using Extensible Processors
18th. IEEE International Conference on VLSI Design, VLSI 2005 pp. 551-556, 2005
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

A Methodology for Architectural Design of Multimedia Multiprocessor SoCs
IEEE Design and Test of Computers 22(1):18-27, 2005
Tiehan Lv, I. Burak Ozer, Srimat T. Chakradhar, Jiang Xu, Wayne Wolf, Joerg Henkel

2004

REMCode: Relocating Embedded Code for Improving System Efficiency
IEEE Computers and Digital Techniques 151(6):457-465, 2004
A. Janapsatya, Sri Parameswaran Joerg Henkel

High-level Synthesis Using Computation-unit Integrated Memories
International Conference on Computer-Aided Design, ICCAD 2004 pp. 783-790, 2004
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

Power Estimation for Cycle-Accurate Functional Descriptions of Hardware
International Conference on Computer-Aided Design, ICCAD, 2004 pp. 668-675, 2004
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

Power Analysis of System-Level On-Chip Communication Architectures
2nd International Conference on HW/SW Codesign and System Synthesis pp. 236-241, 2004
Kanishka Lahiri, Anand Raghunathan

Cypress: Compression and Encryption of Data and Code for Embedded Multimedia System
IEEE Design and Test Magazine 21(5):406-415, 2004
Haris Lekatsas, Joerg Henkel, Venkata Jakkula, Srimat T. Chakradhar

Automatic Energy Performance Macromodeling of Embedded Software
ACM/IEEE Design Automation Conference - DAC 2004 pp. 99-102, 2004
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha

Distributed Multimedia System Design: A Holistic Perspective
IEEE Design, Automation and Test in Europe Conference and Exhibition, DATE, 2004 2:1342-1347, 2004
Radu Marculescu, Massoud Pedram, Joerg Henkel

A Case Study in Networks-on-Chip Design for Embedded Video
IEEE Design, Automation and Test in Europe Conference and Exhibition, DATE 2004 2:770-775, 2004
Jiang Xu, Wayne Wolf, Joerg Henkel, Srimat T. Chakradhar, Tiehan Lv

MINCE: Matching INstructions using Combinational Equivalence for extensible processors
IEEE Design, Automation and Test in Europe Conference and Exhibition, DATE 2004 2:1020-1025, 2004
Newton Cheung, Sri Parameswaran, Joerg Henkel, Jeremy Chan

Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization
IEEE International Conference on VLSI Design, VLSI 2004 pp. 267-272, 2004
Weidong Wang, Anand Raghunathan, Niraj K. Jha

Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips
17th International Conference on VLSI Design, VLSI 2004 pp. 307-315, 2004
Krishna Sekar, Kanishka Lahiri, Sujit Dey

On Chip Networks: a Scalable, Communication Centric Embedded System Design Paradigm
17th. IEEE International Conference of VLSI Design, VLSI 2004 pp. 845-851, 2004
Joerg Henkel, Wayne Wolf, Srimat T. Chakradhar

Energy Optimizing Source Code Transformations for OS-driven Embedded Software
IEEE Conference on VLSI Design, VLSI 2004 pp. 261-266, 2004
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

2003

Synthesis of Heterogeneous Distributed Architectures for Memory-intensive Applications
International Conference on Computer Aided Design, ICCAD 2003 pp. 46-53, 2003
Chao Huang, Srivaths Ravi, Anand Raghunathan

LRU-SEQ: a Novel Replacement Policy for Transition Energy Reduction in Instruction Caches
2003 International Conference on Computer-Aided Design, ICCAD 2003 pp. 518-522, 2003
Praveen Kalla, Xiaobo Sharon Hu, Joerg Henkel

INSIDE: INstruction Selection/Identification and Design Exploration for Extensible Processors
2003 International Conference on Computer Aided Design, ICCAD 2003 pp. 291-297, 2003
Newton Cheung, Sri Parameswaran, Joerg Henkel

Closing the SoC Design Gap
Computer 36(9):119-121, 2003
Joerg Henkel, NEC Laboratories America

CoCo: A Hardware/Software Platform for Rapid Prototyping of Code Compression Technologies
40th. Design Automation Conference. DAC 2003 pp. 306-311, 2003
Haris Lekatsas, Jorg Henkel, Srimat T. Chakradhar, Venkata Jakkula, Murugan Sankaradas

Taking on the Embedded System Design Challenge
Computer 36(4): 35-37, 2003
Joerg Henkel, Xiaobo Sharon Hu, Shuvra S. Bhattacharyya

Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems
Design, Automation and Test in Europe Conference and Exhibition DATE 2003 pp. 706-711, 2003
Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi

Rapid Configuration and Instruction Selection for an ASIP: A Case Study
Design, Automation and Test in Europe Conference and Exhibition,DATE 2003 pp. 802-807, 2003
Newton Cheung, Joerg Henkel, Sri Parameswaran

SEA: Fast Power Estimation for Micro-Architectures
Asia and South Pacific Design Automation Conference, ASP-DAC 2003 pp. 600-605, 2003
Praveen Kalla, Joerg Henkel, Xiaobo Sharon Hu

Specifications and Design of Multi Million Gate SoCs
16th. International Conference on VLSI Design, VLSI 2003 pp. 18-19, 2003
Ramesh Chandra, Joerg Henkel, Preeti Ranjan Panda, Sri Parameswaran, Loganath Ramachandran