logo

Home


Systems Analysis & Verification



SAT Based Verification Publications


2005

Daijue Tang, Sharad Malik, Aarti Gupta, and C. Norris Ip: Symmetry Reduction in SAT-based Model Checking. In Proceedings of CAV, July 2005.

Mukul R. Prasad, Armin Biere and Aarti Gupta: A Survey of Recent Advances in SAT-based Formal Verification. International Journal on Software Tools for Technology Transfer (STTT), Vol. 7(2):156--173, April 2005.

2002

Malay Ganai and Adnan Aziz: Improved SAT-based Bounded Reachability Analysis. In Proceedings of VLSI Design, 2002.

2001

Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, and Sharad Malik: Partition-based Decision Heuristics for Image Computation using SAT and BDDs. In Proceedings of ICCAD, 2001.

Aarti Gupta, Anubhav Gupta, Zijiang Yang, and Pranav Ashar: Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. In Proceedings of DAC, 2001.

2000

Aarti Gupta, Zijiang Yang, Pranav Ashar, and Anubhav Gupta: SAT-based Image Computation with Application in Reachability Analysis. In Proceedings of FMCAD, 2000.

Publications in Other Areas:

 


NEC Laboratories America, Inc.
Princeton Campus - 4 Independence Way, Suite 200, Princeton NJ 08540   |    Cupertino Campus - 10080 North Wolfe Road, Suite SW3-350, Cupertino, CA 95014
webmaster@nec-labs.com   ©2008 NEC Laboratories America, Inc. All rights reserved. Please Read our Privacy Policy

Website design by Dragonfly Interactive, LLC