Department of Computing Systems Architecture - Patents

 7,784,046 

Automatically Boosting the Software Content of System LSI Designs

Lajolo, M.
Lahiri, K.
Chakradhar, S.T.
Mitra, Abhishek

24-Aug-10

 7,730,373 

Test Data Compression Method for System-On-Chip Using Linear-Feedback Shift Register Reseeding

Wang, Z.
Wang, S.

1-Jun-10

 7,653,670 

Storage-Efficient and Collision-Free Hash-Based Processing Architecture and Method

Hasad, J.
Cadambi, S.
Chakradhar, S.T.

26-Jan-10

 7,610,540 

Method for Generating, from a Test Cube Set, a Generator Configured to Generate a Test Pattern

Balakrishnan, K.
Wang, S.
Wei, W.
Chakradhar, S.T.

27-Oct-09

 7,610,539 

Method and Apparatus for Testing Logic Circuit Designs

Balakrishnan, K.
Wang, S.
Wei, W.
Chakradhar, S.T.

27-Oct-09

 7,610,527 

Test Output Compaction with Improved Blocking of Unknown Values

Wang, S.
Balakrishnan, K.
Chakradhar, S.T.

27-Oct-09

 7,592,935 

Information Retrieval Architecture for Packet Classification

Cadambi, S.
Chakradhar, S.T.

22-Sep-09

 7,581,142 

Method and System Usable in Sensor Networks for Handling Memory Faults

Sultan, F.
Nagarajan, K.
Chakradhar, S.T.
Rengaswamy, R.K.

25-Aug-09

 7,577,540 

Re-configurable Embedded Core Test Protocol for System-On-Chips (SOC) and Circuit Boards

Wang, S.
Chakradhar, S.T.
Balakrishnan, K.J.

18-Aug-09

 7,562,321 

Method and Apparatus for Structured ASIC Test Point Insertion

Wang, S.
Chakradhar, S.

14-Jul-09

 7,529,669 

Voice-Based Multimodal Speaker Authentication Using Adaptive Training and Applications Thereof

Ravi, S.
Raghunathan, A.
Chakradhar, S.T.
Nandakumar, K.

5-May-09

 7,502,378 

Flexible Wrapper Architecture for Tiled Networks on a Chip

Lajolo, M.
Garg, S.

10-Mar-09

 7,484,151 

Method and apparatus for testing logic circuit designs

Balakrishnan, K.
Wang, S.
Wei, W.
Chakradhar, S.

27-Jan-09

 7,474,750 

Dynamic content-aware memory compression and encryption architecture

Lekatsas, H.
Henkel, J.
Chakradhar, S.
Jakkula, V.

06-Jan-09

 7,398,278 

A Prefix Processing Technique for Faster IP Routing

Cadambi, S.
Chakradhar, S.
Shibata, H.

08-Jul-08

 7,313,746 

Test Output Compaction for Responses with Unknown Values

Chao, C.-T.
Wang, S.
Chakradhar, S.

25-Dec-07

 7,313,743 

Hybrid Scan-Based Delay Testing Technique for Compact and High Fault Coverage Test Set

Wang, S.
Liu, X.
Chakradhar, S.

25-Dec-07

 7,302,626 

Test Pattern Compression with Pattern-Independent Design-Independent Seed Compression

Balakrishnan, K.
Wang, S.
Chakradhar, S.

27-Nov-07

 7,302,543 

Compressed Memory Architecture for Embedded Systems

Lekatsas, H.
Henkel, J.
Chakradhar, S.
Jakkula, V.

27-Nov-07

 7,284,176 

Externally-Loaded Weighted Random Test Pattern Compression

Wang, S.
Chakradhar, S.

16-Oct-07

 7,278,123 

System-Level Test Architecture for Delivery of Compressed Tests

Ravi, S.
Raghunathan, A.
Lingappan, L.
Chakradhar, S.
Jha, N.K.

02-Oct-07

 7,260,809 

Power Estimation Employing Cycle-Accurate Functional Descriptions

Ravi, S.
Raghunathan, A.
Zhong, L.
Jha, N.K.

21-Aug-07

 7,222,277 

Improved Test Output Compaction Using Response Shaper

Wang, S.
Chakradhar, S.
Chao, C.-T.

22-May-07

 7,203,935 

Hardware/Software Platform for Rapid Prototyping of Code Compression Technologies

Chakradhar, S.T.
Henkel, J.
Jakkula, V.
Lekatsas, H.
Sankaradas, M.

10-Apr-07

 7,188,323 

Restricted Scan Chain Reordering Technique to Enhance Delay Fault Coverage

Wang, S.
Chakradhar, S.
Li, W.

06-Mar-07

 7,134,100 

Method and Apparatus for Efficient Register-Transfer Level (RTL) Power Estimation

Ravi, S.
Raghunathan, A.
Chakradhar, S.

7-Nov-06

 7,131,081 

Scalable Scan-Path Test Point Insertion Technique

Wang, S.
Chakradhar, S.

31-Mar-06

 7,019,674 

Content-Based InformationRetrieval Architecture

Cadambi S.
Kilian, J.
Ashar, P.
Chakradhar, S.T.

28-Mar-06

 6,978,425 

A Methodology for the Design of High-Performance Communications Architecture for Systems-on-Chips Using Communication Architecture Tuners

Raghunathan, A.
Lakshminarayana, G.
Lahiri, K.
Dey, S.

20-Dec-05

 6,892,292 

Apparatus for one-cycle decompression of compressed data and methods of oepration thereof

 6,886,124 

Low hardware overhead scan based 3-weigh weighted random BIST architectures

 6,880,112 

Method and apparatus for online detection and correction of faults affecting system-on-chip buses

 6,877,053 

High performance communication architecture for circuit designs using probabilistic allocation of resources

 6,865,526 

Method for core-based system-level power modeling using object-oriented techniques

 6,735,744 

Power Mode Based Macro-Models For Power Estimation of Electronic Circuits

 6,732,310 

Peripheral partitioning and tree decomposition for partial scan

 6,694,488 

System for the Design of High-Performance Communication Architecture for System-on-Chips Using Communication Architecture Tuners

 6,691,305 

Object Code Compression Using Different Schemes for Different Instruction Types

 6,622,287 

Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems

 6,583,735 

Method and Apparatus for Adaptive Bus Coding for Low Power Deep Sub-Micron Designs