Department of Computing Systems Architecture - Publications

NEC Laboratories America, Inc., Princeton Campus

2010

S.T. Chakradhar, NEC Laboratories America, M. Sankaradas, NEC Laboratories America, V. Jakkula, NEC Laboratories America, S. Cadami, NEC Laboratories America "A Dynamically Configurable Coprocessor for Convolutional Neural Networks", Accepted - ISCA 2010

M. Becchi, NEC Laboratories America, S. Cadambi, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America, "Enabling Legacy Applications on Heterogeneous Platforms", Accepted - HotPar 2010

S.T. Chakradhar, NEC Laboratories America, A. Raghunathan, Purdue University, "Best-effort Computing: Re-thinking Parallel Software and Hardware", Accepted - DAC 2010

V.K. Chippa, Purdue University, D. Mohapatra, Purdue University, A. Raghunathan, Purdue University, K. Roy, Purdue University, S.T. Chakradhar, NEC Laboratories America "Scalable Effort Hardware Design: Exploiting Algorithmic Resilience for Energy Efficiency", Accepted - DAC 2010

M. Becchi, NEC Laboratories America, S. Byna, NEC Laboratories America, S. Cadambi, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America "Data-Aware Scheduling of Legacy Kernels on Heterogeneous Platforms", Accepted - SPAA 2010,

J. Meng, University of Virginia, NEC Laboratories America, A. Raghunathan, Purdue University, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America, S. Byna, NEC Laboratories America "Exploiting the Forgiving Nature of Applications for Scalable Parallel Execution", Proceedings of IPDPS 2010, IEEE 978-4244-6443-2, 2010

L. Yang, Northwestern University, R. P. Dick, Northwestern University, H. Lekatsas, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America "High-Performance Operating System Controlled Online Memory Compression", ACM Transactions on Embedded Computing, 9(4):30.1-30.28, 2010

L. Yang, Northwestern University, R. P. Dick, Northwestern University, H. Lekatsas, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America "On-Line Memory Compression for Embedded Systems", ACM Transactions on Embedded Computing, 9(3):27.0-27.30, 2010

S. Byna, NEC Laboratories America, J. Meng, NEC Laboratories America, University of Virginia, A. Raghunathan, NEC Laboratories America, Purdue University, S.T. Chakradhar, NEC Laboratories America, S. Cadambi, NEC Laboratories America "Best-effort Semantic Documnet Search on GPUs", Proceedings of GPGPU 2010,pp. 86-93, 2010

2009

M. Sankaradas, NEC Laboratories America, V. Jakkula, NEC Laboratories America, S. Cadambi, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America, I. Durdanovic, NEC Laboratories America, E. Cosatto, NEC Laboratories America, H.P. Graf, NEC Laboratories America "A Massively Parallel Coprocessor for Convolutional Neural Networks", Proceedings of ASAP 2009, pp. 53-60, 2009

X.Tang, NEC Laboratories America, S. Wang, NEC Laboratories America,, "A Self-Diagnosis Technique Using Reed-Solomon Codes for Self-Repairing Chips", Proceedings of DSN 2009, pp. 265-274, 2009

N. Sundaram, NEC Laboratories America,University of California-Berkeley, A. Raghunathan, NEC Laboratories America,Purdue University, S.T. Chakradhar, NEC Laboratories America, "A Massively Parallel FPGA-based Coprocessor for Support Vector Machines", Proceedings of IPDPS 2009, 978-1-4244-3750-4/09, 2009

S. Cadambi, NEC Laboratories America, I. Durdanovic, NEC Laboratories America, V. Jakkula, NEC Laboratories America, M. Sankaradas, NEC Laboratories America, E. Cosatto, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America, H.P. Graf, NEC Laboratories America"A Massively Parallel FPGA-based Coprocessor for Support Vector Machines", Proceedings of FCCM 2009, pp. 115-122, 2009

S.T. Chakradhar, NEC Laboratories America, A. Raghunathan, NEC Laboratories America, J. Meng, NEC Laboratories America and University of Virginia, "Best-Effort Parallel Execution Framework for Recognition and Mining Applications", Proceedings of IPDPS 2009

N. Sundaram, NEC Laboratories America and University of California at Berkeley, A. Raghunathan, NEC Laboratories America, and S.T. Chakradhar, NEC Laboratories America "A framework for efficient and scalable execution of domain-specific templates on GPUs", Proceedings of Date 2009

S. Wang, NEC Laboratories America and W. Wei, NEC Laboratories America, "Machine Learning-Based Volume Diagnosis", Proceedings of Date 2009 pp. 902-905, 2009

2008

H.P. Graf, NEC Laboratories America, S. Cadambi, NEC Laboratories America, I. Durdanovic, NEC Laboratories America, V. Jakkula, NEC Laboratories America, M. Sankaradas, NEC Laboratories America, E. Cosatto, NEC Laboratories America and S.T.Chakradhar, NEC Laboratories America, "A Massively Parallel Digital Learning Processor", Proceedings of NIPS 2008, 2008

S. Wang, NEC Laboratories America and W. Wei, NEC Laboratories America, "Cost Efficient Methods to Improve Performance of Broadcast Scan", Proceedings of ATS 2008 pp. 163-169, 2008

S. Wang, NEC Laboratories America and W. Wei, NEC Laboratories America, "An Efficient Unknown Blocking Scheme for Low Control Data Volume and High Observability", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 27, No. 11, pps. 2039-2052, 2008

L. Yang, Northwestern University, R. P. Dick, Northwestern University, H. Lekatsas, NEC Laboratories America and S. T. Chakradhar, NEC Laboratories America, "Ram For Free", IEEE Spectrum pp. 38-43, 2008

S. Wang, NEC Laboratories America, K.J. Balakrishnan, NEC Laboratories America and W. Wei, NEC Laboratories America, "X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactor", IEEE Transactions on Computers Vol. 57 No. 7; pp. 978-989, 2008

S. Wang, NEC Laboratories America, W. Wei, NEC Laboratories America and S.T. Chakradhar, NEC Laboratories America, "Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns", Proceedings of ETS 2008 pps. 125-130, 2008

J. Thoguluva, NEC Laboratories America, A. Raghunathan, NEC Laboratories America "e;IPSec Acceleration using a Programmable Security processor"e;, Proceedings of DATE 2008 pp. 1148-1153, 2008

S. Medardoni, NEC Laboratories America, M. Lajolo, NEC Laboratories America, D. Bertozzi, University of Ferrara, " Variation tolerant NoC design by means of self-calibrating links", Proceedings of DATE 2008 pp. 1402-1407, 2008

2007

J. Otero, NEC Laboratories America, M. Lajolo, NEC Laboratories America "Rapid Creation of Application Models from Bandwidth Aware Core Graphs", Proceedings of IP 2007, 2007

Mango Chia Tso Chao, National Chiao Tung Univ, Kwang Ting Cheng, University of California, S. Wang, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America and W. Wei, NEC Laboratories America, "A Hybrid Scheme for Compacting Test Responses with Unknown Values", Proceedings of ICCAD 2007, pp. 513-519, 2007

S. Wang, NEC Laboratories America, Z. Wang, Duke University, W. Wei, NEC Laboratories America and S.T. Chakradhar, NEC Laboratories America, "A Low Cost Test Data Compression Technique for High n-Detection Fault Coverage", Proceedings of ITC 2007 pp. 1-10, 2007

S. Wang, NEC Laboratories America, W. Wei, NEC Laboratories America and S. T. Chakradhar, NEC Laboratories America, "A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding", Proceedings of ATS 2007 pp. 79-86, 2007

M. Lajolo, NEC Laboratories America, "Latency Insensitive Design of Heterogeneous Tile Based Networks on Chip", DSD 2007 2007

S. Wang, NEC Laboratories America, "Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST", IEEE Transactions on VLSI pp. 777-789, 2007

M.A. Ghodrat, NEC Laboratories America, K. Lahiri, NEC Laboratories America and A. Raghunathan, NEC Laboratories America, "Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation", Proceedings of DAC 2007 pp. 883-886, 2007

S. Chandra, NEC Laboratories America, K. Lahiri, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and S. Dey, University of California, "System-On-Chip Power Management Considering Leakage Variations", Proceedings of DAC 2007 pp. 877-882, 2007

L. Fang, NEC Laboratories America and K.J. Balakrishnan, NEC Laboratories America, "RTL Test Point Insertion to Reduce Delay Test Volume", Proceedings of VLSI Test Symposium 2007

M. Becchi, Washington University and S. Cadambi, NEC Laboratories America, "Memory-Efficient Regular Expression Search Using State Merging", Proceedings of INFOCOM 2007 np, 2007

Q. Zhou, Rice University and K.J. Balakrishnan, NEC Laboratories America, "Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling", Proceedings of DATE 2007 pp. 39-44, 2007

S. Wang, NEC Laboratories America, W. Wei, NEC Laboratories America and S.T. Chakradhar, NEC Laboratories America, "Unknown Blocking Scheme for Low Control Data Volume and High Observability", Proceedings of DATE 2007 pp. 33-38, 2007

A.C. Nacul, NEC Laboratories America, F. Regazzoni, NEC Laboratories America and M. Lajolo, NEC Laboratories America, "Hardware Scheduling Support in SMP Architectures", Proceedings of DATE 2007 pp. 642-647, 2007

Z. Wang, Duke University and S. Wang, NEC Laboratories America, "SoC Testing Approach LFSR Reseeding and Scan-SliceBased TAM Optimization and Test Scheduling", Proceedings of DATE 2007 pp. 201-206, 2007

N. Aaraj, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "Hybride Architectures for Efficient and Secure Face Authentication in Embedded Systems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15(3):296-308, 2007

A. Muttreja, Princeton University, A. Raghunathan, NEC Laboratories America, S. Ravi, NEC Laboratories America and N. K. Jha, Princeton University, "Automatic Energy/performance Macromodeling of Embedded Software", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(3):542-552, 2007

K. J. Balakrishnan, NEC Laboratories America and N. A. Touba, University of Texas at Austin, "Relationship between Entropy and Test Data Compression", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 26(2):386-395, 2007

S. Wang, NEC Laboratories America and W. Wei, NEC Laboratories America, "A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture", Proceedings of the Asia and South Pacific Design Automation Conference 2007 - ASP-DAC 2007 pp. 810-816, 2007

N. Bansal, NEC Laboratories America, K. Lahiri, NEC Laboratories America and A. Raghunathan, NEC Laboratories America, "Automatic Power Modeling of System-on-Chip Infrastructure IP for System-Level Power Estimation", Proceedings of VLSI 2007 pp. 513-520, 2007

R. Sethurap, NEC Laboratories America, S. Wang, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America and M.L. Bushnell, Rutgers University, "Zero Cost Test Point Insertion Technique for Structured ASICs", Proceedings of VLSI 2007 pp. 357-363, 2007

K.J. Balakrishnan, NEC Laboratories America, "Efficient Test Compression Using Multiple LFSRs and Dictionary Coding", Proceedings of VLSI 2007 pp. 345-350, 2007

2006

S. Wang, NEC Laboratories America, R. Sethuram, NEC Laboratories America, S. T. Chakradhar, NEC Laboratories America and M. L. Bushnell, Rutgers University, "Zero Cost Test Point Insertion Technique to Reduce Test Set Sizes and ATPG Run Time for Structured ASICs", Proceedings of 15th Asian Test Symposium - ATS 2006 pp. 339-346, 2006

F. Sun, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N. K. Jha, Princeton University, "A Scalable Synthesis Methodology for Application-Specific Processors", IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14(11):1175-1188, 2006

S. Chandra, University of California, K. Lahiri, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and S. Dey, University of California, "Considering Process Variations During System-Level Power Analysis", Proceedings of 2006 International Symposium on Low Power Electronics and Design - ISLPED 2006 pp. 342-345, 2006

C. Huang, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "Use of Computation-Unit Integrated Memories in High-level Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(10):1969-1989, 2006

L. Zhong, NEC Laboratories America, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "RTL-Aware Cycle-Accurate Functional Power Estimation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(10):2103-17, 2006

L. Lingappan, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America, N. K. Jha, Princeton University and S. T. Chakradhar, NEC Laboratories America, "Test-volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(10): 2193-2206, 2006

S. Garg, NEC Laboratories America and M. Lajolo, NEC Laboratories America, "C-based Design of a Flexible Wrapper for Tiled Networks on Chip", Proceedings of FORUM on Specification and Design Languages - FDL 06 pp. 185-188, 2006

F. Sun, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N. K. Jha, Princeton University, "Application-specific Custom Heterogeneous Multiprocessor Synthesis Methodology using Extensibe Processors", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(9):1589-1602, 2006

L. Yang, Northwestern University, H. Lekatsas, NEC Laboratories America and R. P. Dick, Northwestern University, "High-Performance Operating System Controlled Memory Compression", Proceedings of IEEE/ACM Design Automation Conference - DAC 2006 3:701-704, 2006

B. Mochocki, University of Notre Dame, K. Lahiri, NEC Laboratories America, S. Cadambi, NEC Laboratories America and X.S. Hu, University of Notre Dame, "Signature-based Workload Estimation for Mobile 3D Graphics", Proceedings of IEEE/ACM Design Automation Conference - DAC 2006 2:592-597, 2006

D. Arora, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America, M. Sankaradass, NEC Laboratories America, N.K. Jha, Princeton University and S.T. Chakradhar, NEC Laboratories America, "Software Architecture Exploration for High-Performance Security Processing on a Multi-processor Mobile SoC", Proceedings of ACM/IEEE Design Automation Conference - DAC 2006 2:496-501, 2006

S. Wang, NEC Laboratories America and S. K. Gupta, University of Southern California, "LT-RTPG: A New Test-Per-Scan BIST TPG for Low Switching Activity", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(8);1565-1574, 2006

Mango Chia Tso Chao, University of California, K.T. Cheng, University of California, S. Wang, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America and W. Wei, NEC Laboratories America, "Unknown Tolerance Analysis and Test Quality Control for Test Response Compaction Compactors", Proceedings of ACM/IEEE Design Automation Conference - DAC 2006 3:1083-1088, 2006

M. Psarakis, University of Piraeus, D. Gizopoulos, University of Piraeus, M. Hatzimihail, University of Piraeus, A. Paschalis, University of Athens, A. Raghunathan, NEC Laboratories America and S. Ravi, NEC Laboratories America, "Systematic Software-Based Self-Test for Pipelined Processors", Proceedings of ACM/IEEE Design Automation Conference - DAC 2006 2:393-398, 2006

S. Garg, NEC Laboratories America and M. Lajolo, NEC Laboratories America, "UML Modeling and Configuration of Tile Based Networks on Chip", Proceedings UML-SoC 2006 Session of DAC 2006 Workshop pp. 1-4, 2006

S. Chandra, NEC Laboratories America, F. Regazzoni, ALaRI University and M. Lajolo, NEC Laboratories America, "Hardware/Software Codesign of an Operating System", Proceedings Work-In-Progress Session of the 18th Euromicro Conference on Real-Time Systems - ECRTS 2006 pp. 21-24, 2006

J. Hasan, NEC Laboratories America, V. Jakkula, NEC Laboratories America, S. Cadambi, NEC Laboratories America and S. T. Chakradhar, NEC Laboratories America, "Chisel: A Storage-Efficient, Collision-Free Hash-based Packet Processing Architecture", Proceedings of The 33rd Annual International Symposium on Computer Architecture - ISCA 06 - Computer Architecture News 34(2):203-215, 2006

J. Xu, Princeton University, W. Wolf, Princeton University, J. Henkel, NEC Laboratories America and S. Chakradhar, NEC Laboratories America, "A Design Methodology for Application Specific Networks-on-Chip", ACM Transactions on Embedded Computing Systems 5(2):263-280, 2006

D. Arora, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "Architectural Enhancements for Secure Embedded Processing", Security and Embedded Systems - NATO Security through Science Series - D - Information and Communications Security Serpanos, Dimitrios, (ed.), IOS Press, 2:18-25, 2006

H. Lekatsas, NEC Laboratories America, J. Henkel, NEC Laboratories America, V. Jakkula, NEC Laboratories America and S.T. Chakradhar, NEC Laboratories America, "A Platform for Designing Secure Embedded Systems", Security and Embedded Systems - NATO Security through Science Series - D - Information and Communications Security Serpanos, Dimitrios, (ed.), IOS Press, 2:73-82, 2006

S. Chandra, NEC Laboratories America, F. Regazzoni, ALaRI University and M. Lajolo, NEC Laboratories America, "Hardware/Software Partitioning of Operating Systems: a Behavioral Synthesis Approach", Proceedings of the 2006 ACM Great Lakes Symposium on VLSI - GLSVLSI 2006 pp. 324-329, 2006

N. Potlapally, Princeton University, A. Raghunathan, NEC Laboratories America, S. Ravi, NEC Laboratories America and N.K. Jha, Princeton University, "A Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software", Proceedings of Design Automation and Test in Europe Conference - DATE 2006 pp. 18-23, 2006

S. Wang, NEC Laboratories America, K.J. Balakrishnan, NEC Laboratories America and S. T. Chakradhar, NEC Laboratories America, "Efficient Unknown Blocking Using LFSR Reseeding", Proceedings of Design Automation and Test in Europe Conference - DATE 2006 pp. 1051-1052, 2006

N. Aaraj, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "Architectures for Efficient Face Authentication in Embedded Systems", Proceedings of Design Automation and Test in Europe Conference - DATE 2006 pp. 1-6, 2006

Mango Chia Tso Chao, University of California, S. Wang, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America, W. Wei, University of California and K.T. Cheng, University of California, "Coverage Loss by Using Space Compactors in Presence of Unknown Values", Proceedings of Design Automation and Test in Europe Conference - DATE 2006 pp. 1053-1054, 2006

B.C. Mochocki, NEC Laboratories America, K. Lahiri, NEC Laboratories America and S. Cadambi, NEC Laboratories America, "Power Analysis of Mobile 3D Graphics", Proceedings of the Design Automation and Test in Europe Conference - DATE 2006 pp. 502-508, 2006

P. Stanley-Marbell, Carnegie Mellon University, K. Lahiri, NEC Laboratories America and A. Raghunathan, NEC Laboratories America, "Adaptive Data Placement in an Embedded Multiprocessor Thread Library", Proceedings of the Design Automation and Test in Europe Conference - DATE 2006 pp. 698-699, 2006

K. Sekar, University of California, K. Lahiri, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and S. Dey, University of California, "Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms", Proceedings of the Design Automation and Test in Europe Conference - DATE 2006 pp. 728-733. 2006

L. Lingappan, Princeton University, S. Ravi, NEC Laboratories America and N. K. Jha, Princeton University, "Satisfiability-Based Test Generation for Nonseparable RTL Controller-Datapath Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(3):544-557, 2006

N. Potlapally, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America, R. Lee, Princeton University and N.K. Jha, Princeton University, "Impact of Configurability and Extensibility on IPsec Protocol Execution on Embedded Processors", Proceedings of 19th. IEEE International Conference on VLSI Design - VLSID 2006 pp. 299-304, 2006

K. J. Balakrishnan, NEC Laboratories America, S. Wang, NEC Laboratories America and S. T. Chakradhar, NEC Laboratories America, "PIDISC: Pattern Independent Design Independent Seed Compression Technique", Proceedings of 19th. IEEE International Conference on VLSI Design - VLSID 2006 pp. 811-817, 2006

H. Lekatsas, NEC Laboratories America, J. Henkel, NEC Laboratories America, V. Jakkula, NEC Laboratories America and S. T. Chakradhar, NEC Laboratories America, "Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems", Proceedings of 19th. IEEE International Conference on VLSI Design - VLSID 2006 pp. 639-644, 2006

F. Sun, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "Hybrid Custom Instruction and Co-processor Synthesis Methodology for Extensible Processors", Proceedings of 19th. IEEE International Conference on VLSI Design - VLSID 2006 pp. 473-476, 2006

A. C. Nacul, University of California, M. Lajolo, NEC Laboratories America and T. Givargis, University of California, "Interface-Centric Abstraction Level for Rapid Hardware/Software Integration", Applications of Specification and Design Languages for SoCs Vachoux, A. (ed.), Dordrecht, Springer, pp. 83-99, 2006

P. Kalla, University of Notre Dame, X.S. Hu, University of Notre Dame and J. Henkel, NEC Laboratories America, "Distance-Based Recent Use (DRU): An Enhancement to Instruction Cache Replacement Policies for Transition Energy Reduction", IEEE Transactions on Very Large Scale Integration Systems - VLSI 14(1):69-80, 2006

2005

K. J. Balakrishnan, NEC Laboratories America, N. A. Touba, University of Texas at Austin and S. Patil, Intel Corporation, "Compressing Functional Tests for Microprocessors", Proceedings of the Asian Test Symposium - ATS 05 pp. 428-433, 2005

K.J. Balakrishnan, NEC Laboratories America, "Emerging Techniques for Test Data Compression", Proceedings of the Asian Test Symposium pp. 462-462, 2005

F. Regazzoni, ALaRI-USI and M. Lajolo, NEC Laboratories America, "Hardware/Software Partitioning and Interface Synthesis in Networks On Chip", Proceedings of the IP Based SoC Design Conference and Exhibition IP-SOC 2005 pp. 291-296, 2005

Mango Chia Tso Chao, University of California, S. Wang, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America and K.T. Cheng, University of California, "Response Shaper: A Novel Technique to Enhance Unknown Tolerance for Output Response Compaction", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design pp. 80-87, 2005

S. Wang, NEC Laboratories America, K.J. Balakrishna n, NEC Laboratories America and S. T. Chakradhar, NEC Laboratories America, "XWRC: Externally-loaded Weighted Random Pattern Testing for Input Test Data Compression", Proceedings of the International Test Conference - ITC pp. 571-580, 2005

C. Huang, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "Generation of Distributed Logic-memory Architectures through High-Level Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(11):1694-1711, 2005

Mango Chia Tso Chao, NEC Laboratories America, S. Wang, NEC Laboratories America, S.T. Chakradhar, NEC Laboratories America and K.T. Cheng, University of California, "ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values", Proceedings of IEEE Conference on Computer Design ICCD pp.147-152, 2005

A. C. Nacul, University of California, T. Givargis, University of California and M. Lajolo, NEC Laboratories America, "Interface-Centric Abstraction Level for Rapid Hardware/Software Integration", Proceedings of FORUM on Specification and Design Languages pp. 329-340, 2005

F. Regazzoni, ALaRI-USI, A.C. Nacul, University of California and M. Lajolo, NEC Laboratories America, "Automatic synthesis of the Hardware/Software Interface in Multiprocessor Architectures", Proceedings of the Forum on specification and Design Languages - FDL'05 pp. 401-404, 2005

J. Coburn, NEC Laboratories America, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and S.T. Chakradhar, NEC Laboratories America, "SECA : Security-enhanced Communication Architecture", Proceedings of the ACM/IEEE Conference on Compilers, Architecture, and Synthesis for Embedded Systems - CASES pp. 78-89, 2005

D. Arora, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "Enhancing Security through Hardware-assisted Run-time Validation of Program Data Properties", Proceedings of ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis pp. 190-195, 2005

C. Huang, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "Eliminating Memory Bottlenecks for a JPEG Encoder Through Distributed Logic-Memory Architecture and Computation-unit Integrated Memory", Proceedings of the 2005 IEEE Custom Integrated Circuits Conference pp. 236-239, 2005

L. Yang, Northwestern University, H. Lekatsas, NEC Laboratories America, R. P. Dick, Northwestern University and S. T. Chakradhar, NEC Laboratories America, "CRAMES : Compressed RAM for Embedded Systems", Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis CODES + ISSS '05 pp. 93-98, 2005

J. Xu, Princeton University, W. Wolf, Princeton University, J. Henkel, NEC Laboratories America and S. Chakradhar, NEC Laboratories America, "H.264 HDTV Decoder Using Application-Specific Networks-on-Chip", Proceedings of IEEE Conference on Multimedia and Expo - ICME 2005 pp. 1508-1511, 2005

A. Muttreja, Princeton University, A. Raghunathan, NEC Laboratories America, S. Ravi, NEC Laboratories America and N.K. Jha, Princeton University, "Hybrid Simulation for Embedded Software Energy Estimation", Proceedings of the 42nd. Annual ACM/IEEE Conference on Design Automation 2005 DAC'05 pp. 23-26, 2005

K. Sekar, University of California, K. Lahiri, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and S. Day, University of California, "FLEXBUS: A High-Performance System-on-Chip Communication Architecture with a Dynamically Configurable Topology", Proceedings of the 42nd. Annual ACM/IEEE Conference on Design Automation 2005 DAC'05 pp. 571-574, 2005

P. Gupta, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "Efficient Fingerprint-based User Authentication for Embedded Systems", Proceedings of the 42nd. Annual ACM/IEEE Conference on Design Automation 2005 DAC'05 pp. 244-247, 2005

J. Coburn, NEC Laboratories America, S. Ravi, NEC Laboratories America and A. Raghunathan, NEC Laboratories America, "Power Emulation: A New Paradigm for Power Estimation", Proceedings of the 42nd. Annual ACM/IEEE Conference on Design Automation 2005 DAC'05 pp. 700-705, 2005

A. S. Basu, NEC Laboratories America, M. Lajolo, NEC Laboratories America and M. Prevostini, ALaRI, "Design and Synthesis of Reusable Platforms with Programmable Interconnects", Proceedings of the DAC 2005 Workshop, UML-SoC 2005, UML for SoC Design pp. 43-48, 2005

H. Lekatsas, CCRL, J. Henkel, CCRL and W. Wolf, Princeton University, "Approximate Arithmetic Coding for Bus Transition Reduction in Low Power Designs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13(6):696-707, 2005

J. Xu, Princeton University, W. Wolf, Princeton University, J. Henkel, NEC Laboratories America, S. Chakradhar, NEC Laboratories America and T. Lv, Princeton University, "A Methodology for Design, Modeling, and Analysis of Networks-on-Chip", Proceedings of IEEE International Symposium on Circuits and Systems ISCAS 2:1778-81, 2005

A. Mitra, NEC Laboratories America /& University of California, M. Lajolo, NEC Laboratories America and K. Lahiri, NEC Laboratories America, "SOFTENIT: A Methodology for Boosting the Software Content of System-on-Chip Designs", Proceedings of the 15th. ACM Great Lakes Symposium on VLSI pp. 361-366, 2005

S. Parameswaran, University of Queensland and J. Henkel, NEC Laboratories America, "Instruction Code Mapping for Performance Increase and Energy Reduction in Embedded Computer systems", IEEE Transactions on Very Large Scale Integration - VLSI 13(4):498-502, 2005

J. Coburn, NEC Laboratories America, S. Ravi, NEC Laboratories America and A. Raghunathan, NEC Laboratories America, "Hardware Accelerated Power Estimation", Proceedings of the Design, Automation and Test in Europe Conference and Exhibition - DATE'05 1:528-529, 2005

L. Lingappan, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America, N.K. Jha, Princeton University and S.T. Chakradhar, NEC Laboratories America, "Heterogeneous and Multi-level Compression Techniques for Test Volume Reduction in Systems-on-chip", Proceedings of the 18th. IEEE International Conference on VLSI Design pp. 65-70, 2005

N. Bansal, NEC Laboratories America, K. Lahiri, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and S.T. Chakradhar, NEC Laboratories America, "Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models", Proceedings of the 18th. IEEE International Conference on VLSI Design 2005 pp. 575-585, 2005

H. Lekatsas, NEC Laboratories America, J. Henkel, NEC Laboratories America, V. Jakkula, NEC Laboratories America and S.T. Chakradhar, NEC Laboratories America, "A Unified Architecture for Adaptive Compression of Data and Code for Embedded Systems", Proceedings of the 18th. IEEE International Conference on VLSI Design pp. 117-123, 2005

F. Sun, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N. K. Jha, Princeton University, "Synthesis of Application-specific Heterogeneous Multiprocessor Architectures using Extensible Processors", Proceedings of the 18th. IEEE International Conference on VLSI Design, 2005 pp. 551-556, 2005

T. Lv, Princeton University, J. Xu, Princeton University, W. Wolf, Princeton University, I.B. Ozer, Princeton University, J. Henkel, NEC Laboratories America and S. Chakradhar, NEC Laboratories America, "A Methodology for Architectural Design of Multimedia Multiprocessor SoCs", IEEE Design and Test of Computers 22(1):18-27, 2005

2004

A. Janapsatya, University of New South Wales, S. Parameswaran, University of New South Wales and J. Henkel, NEC Laboratories America, "REMCode: Relocating Embedded Code for Improving System Efficiency", IEE Proceedings Computers and Digital Techniques 151(6):457-465, 2004

C. Huang, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "High-level Synthesis Using Computation-unit Integrated Memories", Proceedings of the International Conference on Computer-Aided Design, ICCAD 2004 pp. 783-790, 2004

L. Zhong, NEC Laboratories America, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "Power Estimation for Cycle-Accurate Functional Descriptions of Hardware", ACM/IEEE Proceedings of the International Conference on Computer-Aided Design, ICCAD, 2004 pp. 668-675, 2004

K. Lahiri, NEC Laboratories America and A. Raghunathan, NEC Laboratories America, "Power Analysis of System-Level On-Chip Communication Architectures", Proceedings of the 2nd International Conference on HW/SW Codesign and System Synthesis pp. 236-241, 2004

H. Lekatsas, NEC Laboratories America, J. Henkel, NEC Laboratories America, V. Jakkula, NEC Laboratories America and S.T. Chakradhar, NEC Laboratories America, "Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems", IEEE Design and Test Magazine 21(5):406-415, 2004

A. Muttreja, Princeton University, A. Raghunathan, NEC Laboratories America, S. Ravi, NEC Laboratories America and N. K. Jha, Princeton University, "Automatic Energy Performance Macromodeling of Embedded Software", Proceedings of the ACM/IEEE Design Automation Conference - DAC 2004 pp. 99-102, 2004

R. Marculescu, Carnegie Mellon University, M. Pedram, University of Southern California and J. Henkel, NEC Laboratories America, "Distributed Multimedia System Design: A Holistic Perspective", IEEE Design, Automation and Test in Europe Conference and Exhibition, DATE, 2004 2:1342-1347, 2004

J. Xu, Princeton University, W. Wolf, Princeton University, J. Henkel, NEC Laboratories America, S. Chakradhar, NEC Laboratories America and T. Lv, Princeton University, "A Case Study in Networks-on-Chip Design for Embedded Video", Proceedings of the IEEE Design, Automation and Test in Europe Conference and Exhibition DATE, 2004 2:770-775, 2004

N. Cheung, University of New South Wales, S. Parameswaran, University of New South Wales, J. Henkel, NEC Laboratories America and J. Chan, University of New South Wales, "MINCE: Matching INstructions using Combinational Equivalence for extensible processors", IEEE Design, Automation and Test in Europe Conference and Exhibition DATE, 2004 2:1020-1025, 2004

W. Wang, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N. Jha, Princeton University, "Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization", Proceedings of the IEEE International Conference on VLSI Design pp. 267-272, 2004

K. Sekar, University of California, K. Lahiri, NEC Laboratories America and S. Dey, University of California, "Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips", Proceedings of the 17th International Conference on VLSI Design pp. 307-315, 2004

J. Henkel, NEC Laboratories America, W. Wolf, Princeton University and S.T. Chakradhar, NEC Laboratories America, "On Chip Networks: a Scalable, Communication Centric Embedded System Design Paradigm", Proceedings of the 17th. IEEE International Conference of VLSI Design pp. 845-851, 2004

Y. Fei, Princeton University, S. Ravi, NEC Laboratories America, N. Jha, Princeton University and A. Raghunathan, NEC Laboratories America, "Energy Optimizing Source Code Transformations for OS-driven Embedded Software", Proceedings of the IEEE Conference on VLSI Design pp. 261-266, 2004

2003

C. Huang, Princeton University, S. Ravi, NEC Laboratories America, A. Raghunathan, NEC Laboratories America and N.K. Jha, Princeton University, "Synthesis of Heterogeneous Distributed Architectures for Memory-intensive Applications", Proceedings of the International Conference on Computer Aided Design pp. 46-53, 2003

P. Kalla, University of Notre Dame, X.S. Hu, University of Notre Dame and J. Henkel, NEC Laboratories America, "LRU-SEQ: a Novel Replacement Policy for Transition Energy Reduction in Instruction Caches", Proceedings of the 2003 International Conference on Computer-Aided Design pp. 518-522, 2003

N. Cheung, University of New South Wales, S. Parameswaran, University of New South Wales and J. Henkel, NEC Laboratories America, "INSIDE: INstruction Selection/Identification and Design Exploration for Extensible Processors", Proceedings of the 2003 International Conference on Computer Aided Design pp. 291-297, 2003

J. Henkel, NEC Laboratories America, "Closing the SoC Design Gap", Computer 36(9):119-121, 2003

H. Lekatsas, NEC Laboratories America, J. Henkel, NEC Laboratories America, S. T. Chakradhar, NEC Laboratories America, V. Jakkula, NEC Laboratories America and M. Sankaradass, NEC Laboratories America, "CoCo: A Hardware/Software Platform for Rapid Prototyping of Code Compression Technologies", Proceedings of the 40th. Design Automation Conference pp. 306-311, 2003

J. Henkel, NEC Laboratories America, X.S. Hu, University of Notre Dame and S. S. Bhattacharyya, University of Maryland, "Taking on the Embedded System Design Challenge", Computer 36(4): 35-37, 2003

D. Bertozzi, University of Bologna, A. Raghunathan, NEC Laboratories America, L. Benini, University of Bologna and S. Ravi, NEC Laboratories America, "Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems", Proceedings of the Design, Automation and Test in Europe Conference and Exhibition 2003 pp. 706-711, 2003

N. Cheung, University of New South Wales, J. Henkel, NEC Laboratories America and S. Parameswaran, University of New South Wales, "Rapid Configuration and Instruction Selection for an ASIP: A Case Study", Proceedings of the Design, Automation and Test in Europe Conference and Exhibition 2003 pp. 802-807, 2003

P. Kalla, University of Notre Dame, J. Henkel, NEC Laboratories America and X.S. Hu, University of Notre Dame, "SEA: Fast Power Estimation for Micro-Architectures", Proceedings of the Asia and South Pacific Design Automation Conference, 2003 ASP-DAC 2003 pp. 600-605, 2003

R. Chandra, ST Microelectronics, J. Henkel, NEC Laboratories America, P.R. Panda, Indian Institute of Technology, S. Parameswaran, University of New South Wales and L. Ramachandran, Synopsys, "Specifications and Design of Multi Million Gate SoCs", Proceedings of the 16th. International Conference on VLSI Design 2003 pp. 18-19, 2003