NEC Laboratories America, Inc.

Aarti Gupta

Aarti Gupta

NEC Laboratories America, Inc.
4 Independence Way, Suite 200
Princeton, NJ 08520
+1 (609) 951-2966
Email: agupta at nec-labs dot com

Research Interests

Software Verification: software model checking, program analysis, static analyzers, model-based development, software testing
Formal Verification: model checking, abstraction-refinement, equivalence checking, hardware verification
Automatic Decision Procedures: Boolean Satisfiability (SAT) solvers, Satisfiability Modulo Theory (SMT) solvers, Binary Decision Diagrams (BDDs)
Electronic Design Automation: specification and verification languages, semi-formal verification, simulation-based validation

Publications

Invited Talks

VSW 2012: Detecting Concurrency Bugs using Static and Dynamic Analyses. Verified Software Workshop and Summer School, Shanghai, August 2012.
FMCAD 2011: Verifying Concurrent Programs. Invited Tutorial, FMCAD Conference, October 2011.
SuRI 2011: Coping with Multi-thread Schedules for Detecting Concurrency Bugs. Summer Research Institute (SuRI), EPFL, June 2011.
SuRI 2011: Scalable Software Model Checking for Finding Bugs in the Large. Summer Research Institute (SuRI), EPFL, June 2011.
FMICS 2010: Coping with Multi-thread Schedules. International Workshop on Formal Methods for Industry Critical Systems, September 2010.
VMCAI 2009: Model Checking Concurrent Multi-threaded Programs
IJCAR 2008: Software Verification: Roles and Challenges for Automatic Decision Procedures
HVC 2007: From Hardware Verification to Software Verification: Re-use and Re-learn
IBM IRL Workshop 2006: Enhancing Model Checking with Static Code Analysis for Verifying Programs
SSPV 2006: Verifying C Programs using SAT-based model checking
SFM 2006: SAT-based Hardware Verification

Professional Activities

2013: PLDI (ERC), WODA (Workshop on Dynamic Analysis), VSTTE.
2012: POPL, CAV, TACAS, PLDI (ERC), Alan Turing Centenary Conference (Turing 100), FMCAD, APLAS.
2011: VMCAI, SPIN, FMCAD, RV.
2010: SMT, VLSI Design, HVC, Workshop on Model Checking and Artificial Intelligence (MoChArt), FMICS, FMCAD.
2009: TACAS, CAV, FMCAD.
2008: CAV, TACAS, SAT, FMCAD, HVC.
2007: DATE, SAT, FMCAD, ATVA, FSTTCS, HVC, SMT Workshop.
2006: FMCAD, DATE, BMC Workshop, Workshop on Software Verification and Validation (SVV), HVC.
Others: DATE 2005, Workshop on Constraints for Verification (2005, 2004), CAV 2004, VLSI Design, 2004, ICCAD (2003, 2002, 2001).

Steering Committee, Formal Methods in Computer Aided Design (FMCAD): since 2007
CAV Award Committee: since 2012
Co-Chair, International Workshop on Satisfiability Modulo Theories (SMT 2010)
Co-Chair, International Conference on Computer Aided Verification (CAV 2008)
Co-Chair, International Conference on Formal Methods in Computer Aided Design (FMCAD 2006)

Associate Editor, Formal Methods in System Design, Springer: since 2005
Associate Editor, ACM Transactions on Design Automation of Electronic Systems (TODAES): 2008-2012

Other Information