Phone:  (609) 951-2835

I am a researcher in the System Architecture department at NEC Laboratories America, Princeton, NJ. My primary interest is computer architecture, especially special-purpose, reconfigurable and fault-tolerant architectures. Over the past few years at NEC Labs, I have worked on a hardware accelerator for logic simulation (SimPLE) and a hash-based lookup engine for networking. SimPLE has since spun-off as an independent start-up.

I am currently working on massively parallel hardware architectures for machine learning applications. I have also briefly worked on transactional memory hardware for multi-cores.

Before arriving at NEC Labs in 2000, I got my Ph.D.from Carnegie Mellon's Electrical and Computer Engineering Department, where I was part of a research group working on a reconfigurable architecture called PipeRench. Prior to that, I obtained an M.S. from the University of Massachusetts Amherst, which I joined after graduating from the Indian Institute of Technology, Madras in 1993. And even before that, what now seems like such a long time ago, I lived in Bangalore, India, where I did most of my growing up and schooling.



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