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Snail
Mail:
4 Independence Way, Ste 200
Princeton, NJ 08540
Phone: 609-951-2973
Fax: 609-951-2483
Email: malay
at nec-labs.com
Resume:
pdf
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Malay K. Ganai
Senior Research
Staff Member
System LSI and Software Verification
NEC Laboratories
America
Malay K Ganai received B.Tech
in Electrical Engineering from IIT Kanpur, India in 1992; MS degree and Ph.D.
degree in Electrical and Computer Engineering from the University
of Texas at Austin, USA
in 1999 and 2001, respectively. After graduation, from 1992 to 1995, Malay
worked at Larsen & Toubro on embedded system design projects. In 1995, he
joined Cadence Design Systems, India where he worked until 1997
on various projects involving high-level synthesis and Signal Processing
Workbench (SPW). While at UT Austin as a graduate student, he instrumented a
semi-formal verification tool, SIVA that combines simulation
with symbolic algorithms for efficient state space search. Since 2001, he is
working with NEC Laboratories America in System LSI and Software Verification
group on devising various SAT-based scalable model checking algorithms. He
was recognized with technology commercialization award for being the
principal architect and author of VeriSol (formerly known as DiVer), SAT-based Formal Verification Platform. Currently, VeriSol
is commercially available as C-level Property Checker in NEC’s Cyber Work Bench (CWB). His current research
includes Constraint logic solvers, SAT-based and SMT-based formal
verification methods, Semi-formal verification and Verification methodology, and
error diagnosis.
He has
co-authored a book “SAT-based
Scalable Formal Verification Solutions” in the series of Integrated
Circuits and Systems, published by Springer
(July 2007).
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NEC Laboratories America, Inc.
Princeton Campus
- 4 Independence Way, Suite 200, Princeton NJ 08540
Cupertino Campus
- 10080 North Wolfe Road, Suite SW3-350, Cupertino, CA 95014
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