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US Patents
Issued
Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient modeling of
embedded memories in bounded model checking. Patent # 7,386,818 Issued Jun 10, 2008
Franjo Ivancic, Pranav Ashar, Malay K Ganai, Aarti Gupta, and
Ziiiang Yang: System and Method for Modeling, Abstraction and Analysis of
Software. Patent # 7,326486. Issued Mar 18, 2008.
Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient SAT-based
Unbounded Model Checking. Patent #7,305,637. Issued Dec 04, 2007.
Malay K. Ganai, Aarti Gupta, Ziiiang Yang, and Pranav Ashar:
Efficient Distributed SAT and SAT-based Distributed Bounded Model Checking. Patent # 7,203,917. Issued Apr 10, 2007.
Malay K. Ganai, Geert Janssen, Florian Karl Krohm, Andreas
Kuehlmann, and Viresh Paruthi: Method and system for equivalence-checking
combinatorial circuits using iteractive binary-decision-diagram sweeping and
structural satisfiability analysis. Patent # 6,473,884. Issued Oct 29, 2002.
US Patent Pending
Malay K. Ganai and Sudipta Kundu. Methods and systems for
reducing verification conditions for concurrent programs using Mutually
Atomic Transactions. Patent
Application #20100088680. Filed Sept 29, 2009.
Malay K. Ganai. Parallelizing Bounded Model Checking using
Tunnels over a distributed framework. Patent
Application #20100011057. Filed Sept 24, 2008.
Malay K. Ganai and Gogul Balakrishnan. Proof-guided error diagnosis
(PED) by triangulation of program error causes. Patent
application #20090292941. Filed Dec 9, 2008.
Malay K. Ganai. Efficient Decision Procedure for Bounded Integer
Non-linear operations using SMT(LIA). Patent
application #20090222393. Filed Dec 9, 2008.
Malay K. Ganai and Sudipta Kundu. Partial order reduction for
scalable testing in system level design. Patent
application #20090132991. Filed Nov 5, 2008.
Malay K. Ganai. System and Method for Tunneling and Slicing based
BMC decomposition. Patent
Application #20090125294, Filed July 31, 2008.
Malay K. Ganai and Aarti Gupta. Modeling and Verification of Concurrent Systems
using SMT-based BMC. Patent Application #20080281563. Filed May 7,
2008.
Malay K. Ganai and Aarti Gupta. High-level Synthesis for
Efficient Verification. Patent Application #20070226666. Filed Sep 27,
2007.
Malay K. Ganai and Aarti Gupta. Accelerating High-level Bounded
Model Checking. Patent Application #20070226665. Filed. Filed
Sep 27, 2007.
Hari Cadambi, Alexandr Zaks, Fanjo Ivancic, Ilya Shlyaktar, Zijiang
Yang, Malay K. Ganai, Aarti Gupta, and Pranav Ashar. Software Verfication
using Range Analysis. Patent application #20060282806. Filed Dec 14,
2006.
Franjo Ivancic, Aarti Gupta, Malay Ganai, Himanshu Jain. Software
Verification. Patent Application #20060282807. Filed Dec 14,
2006.
Malay K. Ganai, Lintao Zhang, Aarti Gupta, Ziiiang Yang, and
Pranav Ashar: Efficient Approaches for Bounded Model Checking. Patent Application # 20030225552. Filed May 30,
2002.
Aarti Gupta, Malay K. Ganai, Ziiiang Yang, and Pranav Ashar:
Iterative Abstraction using SAT-based BMC Proof Analysis. Patent Application # 20040230407. Filed Jan
23, 2004.
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