Jiawei Zhang works at Princeton University.

Posts

Link Loss Analysis of Integrated Linear Weight Bank within Silicon Photonic Neural Network

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Over the last decade, silicon photonic neural networks have demonstrated the possibility of photonic-enabled machine learning at the edge. These systems enable low-latency ultra-wideband classifications, channel estimations, and many other signal characterization tasks within wireless environments. While these proof-of-concept experiments have yielded promising results, poor device and architectural designs have resulted in sub-optimal bandwidth and noise performance. As a result, the application space of this technology has been limited to GHz bandwidths and high signal-to-ratio input signals. By applying a microwave photonic perspective to these systems, the authors demonstrate high-bandwidth operation while optimizing for RF performance metrics: instantaneous bandwidth, link loss, noise figure, and dynamic range. The authors explore the extended capabilities due to these improved metrics and potential architectures to continue further optimization. The authors introduce novel architectures and RF analysis for RF-optimized neuromorphic photonic hardware.

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A system-on-chip microwave photonic processor solves dynamic RF interference in real-time with femtosecond latency

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Radio-frequency interference is a growing concern as wireless technology advances, with potentially life-threatening consequences like interference between radar altimeters and 5?G cellular networks. Mobile transceivers mix signals with varying ratios over time, posing challenges for conventional digital signal processing (DSP) due to its high latency. These challenges will worsen as future wireless technologies adopt higher carrier frequencies and data rates. However, conventional DSPs, already on the brink of their clock frequency limit, are expected to offer only marginal speed advancements. This paper introduces a photonic processor to address dynamic interference through blind source separation (BSS). Our system-on-chip processor employs a fully integrated photonic signal pathway in the analogue domain, enabling rapid demixing of received mixtures and recovering the signal-of-interest in under 15 picoseconds. This reduction in latency surpasses electronic counterparts by more than three orders of magnitude. To complement the photonic processor, electronic peripherals based on field-programmable gate array (FPGA) assess the effectiveness of demixing and continuously update demixing weights at a rate of up to 305?Hz. This compact setup features precise dithering weight control, impedance-controlled circuit board and optical fibre packaging, suitable for handheld and mobile scenarios. We experimentally demonstrate the processor’s ability to suppress transmission errors and maintain signal-to-noise ratios in two scenarios, radar altimeters and mobile communications. This work pioneers the real-time adaptability of integrated silicon photonics, enabling online learning and weight adjustments, and showcasing practical operational applications for photonic processing.

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